CMOS technology is used in semiconductor manufacturing. Due to the stringent requirements imposed over the past years in terms of density scaling, on-chip functionality, and device performance, new device alternatives, as well as the integration of new materials, are being explored.
Amongst the new materials currently explored, III-V materials attract much interest. III-V materials have a few characteristics making them better suited to some applications than Si. Such III-V material characteristics include the presence of a direct band-gap, which permits the emission of light and hence their use in light emitting diodes (LEDs) but also the detection of light and their use in light sensors; their thermal stability and high dielectric strength which makes them useful in high-power electronics (e.g. radio frequency high electron mobility transistors, RF-HEMT); and their wide band gap which has been put to use in microelectromechanical systems (MEMS). However, integration of III-V materials with Si remains a challenge.
While tunneling field effect transistors (TFET) have been attracting much attention to be one of the potential alternative devices to replace MOSFET technology in the sub-10 nm regime for low-power applications, integration of Group III-V materials as channel layer material in these devices has been the focus of research and development in the semiconductor industry.
A Group III-nitride tunnel junction, such as for example In(Ga)N/GaN tunnel junction (TJ), could be a potential candidate for the TFET application, due to the high band offset between InN and GaN and their direct band diagram. However, there are several challenges for the realization of In(Ga)N/GaN complementary TFET devices including the challenge of monolithic integration of III-N material and devices with CMOS technology and the high defects density of III-N materials when growing on Si substrates, which can dramatically increase the gate leakage of the TFET.
On the other hand, the integration Group III-V channel layer materials, the lattice mismatch between InP and In(Ga) As with Si, which is respectively of about 8% and 12%, poses a challenge. Although several growth technology options, such as aspect ratio trapping (ART), can help to make functional devices based on InGaAs/InP material systems, there are still several disadvantages that are difficult to overcome. Some of these challenges being, for example, the high cost of the TBP precursor and high flow of NH3 (with high V/III ratio) to grow high-quality InP buffer increases the manufacturing cost. In addition, the poor thermal and chemical stability of InGaAs/InP makes it very difficult to integrate with other standard CMOS fabrication technologies. Furthermore, there is a high risk of contamination for the introduction of InGaAs/InP to the CMOS process line because of their chemical instability issues. Furthermore, because of the low energy bandgap of InGaAs/InP, there is high leakage from drain to Si buffer in the InGaAs/InP FINFET. Another challenge is that scaling capability and device performance improvement are limited by the material physical limitation of InGaAs/InP inside trenches. The narrower the InGaAs FIN, the less the carrier mobility.
Therefore, there is still a need in the art for methods for forming semiconductor structure for resolving some or all of these issues outlined above.